Description of the Related Art
Pixel clock frequency plays an integral role in video format design, as it provides timing for video signals. Typically, for video equipment capable of producing several different video formats, pixel clock synthesis is done using a phase-locked loop (PLL) where a divide by N counter is inserted in the timebase reference path, and a divide by M counter (multiplier) is inserted in the PLL feedback path to form a classic M/N PLL synthesizer. There are typically limitations on the magnitude of the M and N numerical values, in order to keep the PLL locked and the clock jitter-free.
In classical M/N PLL synthesizers, the input frequency reference, divided by the maximum value of N, determines the minimum step in frequency between two settings of the PLL. This is often referred to as channel spacing.
FIG. 1
Most PLL circuits for simple   M  NPLL architecture to achieve channel spacing. FIG. 1 illustrates a conventional phase lock loop (PLL) 100, in which phase locking of two signals, an external signal 116 and a local signal 110, takes place. Phase lock loop 100 includes a phase difference detector 102, a loop filter 104, a clock generator 106, which may be a Voltage controlled Oscillator (VCO). The PLL also includes a predivider 100 and a feedback frequency divider 108, which actually acts as a frequency multiplier. A PLL may also have a clock generator, such as a crystal (not shown).
Phase difference detector 102 determines the phase difference between local signal 110 and an external signal 116. External signal 116 may be received from an external signal source. If the value of actual phase difference signal is equal to zero, local signal 110 is locked in phase with external signal. If the value of actual phase difference signal is not equal to zero, local signal 110 is not locked in phase with external signal, and the frequency of local signal 110 needs to be corrected in order to affect the phase of local signal 110 relative to external signal 116. Clock generator 108, which may be a voltage controlled oscillator (VCO), creates a local signal 110.
This frequency, in conjunction with an m-over-n frequency multiply/divide internal to clock generator 108, sets the overall target frequency of local clock signal 110. Clock input frequency division is accomplished by means of a frequency predivider 100, also referred to as the N internal divider. The Frequency Divider, also referred to as the M internal feedback multiplier 110, which connects to the feedback loop of the PLL, multiplies the incoming external clock. In the PLL closed loop, the effect of the frequency divider is to multiply the PLL input frequency by its Division Factor.
It is desirable for the channel spacing to be very small, in order to accurately control the video frame rate. However, the limited range of M, N values in pixel clock synthesizers has not allowed channel spacing to be small as would be needed to achieve accurate control of video frame rate.